a) Field of the Invention
The present invention relates to a semiconductor device and its manufacturing method, and more particularly to a semiconductor device and its manufacturing method wherein a plurality of contact holes are formed in an interlayer insulating film having a flat surface, and wiring layers filled in the contact holes are formed.
b) Description of the Related Art
An integrated circuit MOS transistor manufacturing method conventionally proposed is illustrated in FIGS. 9 and 10.
At the manufacturing step illustrated in FIG. 9, a field insulating film 12 is formed on the surface of a semiconductor substrate made of such as p-type Si, by a selective oxidization process, the field insulating film 12 being patterned to define active regions. A gate oxide film 14 is then formed on the surface of the active region by thermally oxidizing the substrate surface or by other means. A gate electrode layer 16 is formed on the substrate by depositing polycrystalline Si and patterning it. By using the gate electrode layer 16 and field insulating film 12 as a mask, impurity ions are implanted to form an n.sup.+ -type source region 18 and drain region 20.
Next, an interlayer insulating film 22 having a flat surface is formed on the substrate. This insulating film 22 may be formed, for example, by a combination of an insulating film deposited by CVD (chemical vapor deposition) method and an insulating film coated by spin coating. A resist layer 24 is then formed on the substrate, and holes 24s, 24g, and 24d for the source, gate, and drain are formed in the resist layer 24 by photolithography.
At the next manufacturing step illustrated in FIG. 10, the interlayer insulating film 22 is etched by dry etching using the resist layer 24 as the mask to form contact holes 22s, 22g, and 22d for the source, gate, and drain. In this case, the gate insulating film 14 at the regions corresponding to the contact holes 22s and 22d are also etched to expose the contact areas of the regions 18 and 20. After removing the resist layer 24, a wiring material is deposited and patterned on the substrate to form a source wiring layer, a gate wiring layer, and a drain wiring layer, respectively connected via the contact holes 22s, 22g, and 22d to the region 18, gate electrode layer 16, and region 20.
The above conventional method is, however, associated with the disadvantages of increasing a size of the contact hole 22g and reducing a thickness of the gate electrode layer 16, because a thickness of the interlayer insulating film 2 above the gate electrode layer 16 is thinner than that of the source and drain regions 18 and 20 so that the inside of the contact hole 22g is excessively etched until the contact holes 22s and 22d reach the regions 18 and 20 after the contact hole 22g reached the gate electrode layer 16. Such disadvantages become conspicuous when the aspect ratio of a contact hole increases because of a smaller hole area caused by finer integration.